Job description

Student Project/Internship (6 months)

Proof of Concept for JTAG driven DFT implementation

Project Description

Current DFT (scan) implementation requires several external control pins that can be difficult to allocate in low pin count implementation. The addition of MBIST to the test mode introduce even more requirement for additional control pins to control test mode in an efficient way without using CPU core to handle this.

The goal of this internship is to test implementation of register controlled test mode management using a JTAG interface to write in the test registers. Define multiple test modes via JTAG and verify mode selection in simulations. Although JTAG introduces extra pins, but most of the designs contains a JTAG interface that can also be used for DFT test modes.

The project will be divided in the following steps:

1. Training on DFT implementation in an existing design under the control of a DFT expert
2. Documentation around JTAG controlled DFT implementation.
3. Define and make the strategy reviewed on the existing DFT strategy
4. Implement the solution and compare runtime and pin count compared to the original pin controlled implementation
5. Document the job done with pro & cons